Two New Topologies for Low-Power Half-Adder in 180nm CMOS Technology

This article presents the design of two half-adder with ultra-optima design parameters. In the first idea, half-adder has low power consumption, low propagation delay, and as a result, it has low PDP and EDP. The second design is based on multiplexer circuit. This half-adder in addition to occupying a low space, it has a very low PDP and EDP. It is noteworthy that for drawing circuit schema and designing them HSPICE software is used. The designation is done in 0.18µm technology.

Transmission gate; Power consumption; Pass Transistor; Propagation delay.