Ultra-High Speed Multiplier Based on a Novel Structure

This paper presents a low power and high speed multiplier based on a novel structure. Which the main advantage this structure has the lowest adder unit count, consumption power, and propagation delay. In this paper is simulated some of common structures of multiplier by using 28T full adder cell. We have compared some of the most common multiplier structures like Array multiplier, RCA multiplier, Braun multiplier, Bypassing RCA, Bypassing CSA, and proposed structure of multiplier. From the analysis of these simulated results, it was found that the proposed multiplier structure gives the best performance in terms of power, propagation delay, latency and throughput than other published results. Intensively, HSPICE simulation shows that the new structure consumes 24% less power than Bypassing RCA multiplier, moreover its propagation delay and adder units count 31.63% and 8.34% lower than Bypassing RCA multiplier respectively. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage. The proposed design is suitable for low power and high speed arithmetic applications.

Multiplier