Designing smaller area, low power consumption, low PDP and high speed full adder is always in demand. There are growing requests for low-power and high speed full adders in several applications of computing systems such as computer graphics, scientific computing and image processing. As the channel length tends to the nanoscale regime, the use of MOSFET as a basic device in the full adder achieves its functional limitations such as average power dissipation and speed. In this paper, a 1-bit full adder cell is proposed using a CNTFET transistor with a supply voltage of 0.5V for mobile applications. Using HSPICE software, all the main full adder parameters such as leakage power, average power consumption, delay and power delay product (PDP) were measured. In this study, leakage power of 33.5pW, delay of 123.71ps, average power consumption of 93nW and PDP of 11.51×10-21 J were obtained.
کلید واژگان :Full adder (FA); Ultra low-power; PDP (power-delay product); CNTFET transistor; Mobile applications
ارزش ریالی : 300000 ریال
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جزئیات مقاله
- کد شناسه : 6165806951984963
- سال انتشار : 2020
- نوع مقاله : مقاله کامل پذیرفته شده در کنفرانس ها
- زبان : انگلیسی
- محل پذیرش : IEEE 5th Conference on Technology In Electrical and Computer Engineering (ETECH 2020)
- برگزار کنندگان : Information and Communication Technology (ICT) Tehran, Iran
- تاریخ ثبت : 1401/04/26 19:21:59
- ثبت کننده : امیر باغی رهین
- تعداد بازدید : 116
- تعداد فروش : 0