Analysis and design of dynamic comparators in ultra-low supply voltages

The need for ultra-low power and area-efficient analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV) dynamic clocked comparators to maximize power efficiency and speed. In this paper, a delay analysis for a conventional body-driven LV dynamic comparator is presented. Then based on the analysis results, the circuit of a conventional body-driven comparator is modified for fast operation even in small supply voltages. Simulation results in 90nm CMOS technology reveal that comparator delay time is remarkably reduced. The maximum clock frequency of the proposed comparator can be increased to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming 2.3μW and 184nW, respectively. The standard deviation of the input-referred offset voltage is 5.1mV at 0.5V supply

Low-voltage design, Body-driven dynamic comparators, Low-power design, Delay Analysis